The technical difficulties of high-frequency switching power supplies focus on the deep contradiction between high frequency, high power density, and system reliability, involving multiple engineering challenges at the material, device, circuit, and system levels. The following are the six core difficulties recognized by the current industry:

1. Difficulty in meeting EMI/EMC design standards

The high-frequency switch action generates wideband conduction and radiation noise, which is the biggest obstacle for power supplies to pass CISPR 32, 3C and other certifications.

Main sources of interference: voltage spikes caused by parasitic inductance in power loops, reverse recovery current of diodes, distributed capacitance coupling of high-frequency transformers, and radiation from SW nodes.

Design bottleneck:

The power loop area needs to be controlled within 5cm 2, but high-density layout is difficult to achieve

Traditional LC filters have insufficient ability to suppress radiation>30MHz

Chaotic grounding strategy leads to a significant increase in common mode noise

Typical rectification plan: Ground shielding, RC absorption network, common mode inductor+π - type filter, reserved ≥ 5mm high-voltage isolation tape

2. The driving and dynamic testing of wide bandgap devices (GaN/SiC) are complex

The switching speed of GaN/SiC devices can reach 10-50 V/ns, and traditional silicon device driving schemes are completely ineffective.

Core difficulties:

Gate crosstalk: High dv/dt causes adjacent MOSFETs to erroneously turn on, requiring Kelvin source drive to separate current and voltage circuits

Negative pressure shutdown requirement: SiC requires a shutdown voltage of -3V to -5V to prevent accidental triggering

Measurement distortion: Ordinary differential probes cannot accurately capture Vds waveforms under high common mode voltage, and specialized high-voltage differential probes or optical isolation probes are required

Verification method: Double pulse testing (DPT) has become an industry standard for quantifying on/off losses, reverse recovery characteristics, and crosstalk amplitude

3. The design of magnetic components relies on experience, and there is a large deviation between simulation and actual measurement

At high frequencies, the behavior of magnetic cores and windings is highly nonlinear, and there is often a significant deviation between theoretical calculations and actual performance.

Magnetic core loss: Non sinusoidal excitation (square wave/pulse) causes the error of the traditional Steinmetz formula to exceed 30%, and an improved generalized Steinmetz formula (IGSE) is needed

Winding loss: Eddy current effect increases with frequency squared, copper foil thickness needs to be optimized to 50-100 μ m, multi-layer staggered winding reduces eddy current

Leakage inductance control: Leakage inductance causes voltage spikes, which need to be suppressed through winding segmentation, magnetic core air gap opening, and RCD absorption circuit

Material bottleneck: Nanocrystalline alloys have low high-frequency losses, but their cost is 3-5 times that of ferrites, and the processing technology is complex

4. It is difficult to balance the stability and transient response of the feedback loop

Although digital control enhances flexibility, parasitic parameters can cause the loop model to fail, leading to oscillation or delayed response.

Key indicators:

Phase margin: required to be ≥ 45 °, gain margin ≥ 10dB

Traverse frequency: usually set to 1/5-1/10 of the switching frequency

Engineering Challenge:

Output capacitance ESR, PCB routing inductance, and feedback path parasitic capacitance all affect compensation network design

When the load undergoes a step change (such as the CPU transitioning from no-load to full load), if the voltage drops by more than ± 5%, it is considered a failure

Verification method: The stability of the loop must be verified through Bode plot testing, and simulation alone is unreliable

5. Low precision of multi module parallel current sharing control

To achieve high power output, the system often adopts an N+1 redundant parallel architecture, but current sharing errors can easily lead to uneven thermal stress.

Mainstream methods: output impedance method (slope control), master-slave control, democratic current sharing

Core difficulties:

Component tolerances between modules (such as inductors, MOSFET Rds (on)) result in differences in output impedance

The traditional method is open-loop regulation, which has slow dynamic response and a current sharing error of over 15% during sudden load changes

Current sampling introduces losses (sampling resistance) or costs (Hall sensor)

Innovative solution: Utilizing inductance ESR for non-destructive current sampling, simplifying circuit structure

6. High frequency filtering bottleneck under the design of electrolytic capacitors

To improve lifespan and reliability, high-end power supplies are gradually phasing out electrolytic capacitors, but ceramic capacitors have extremely low ESR, leading to a decrease in high-frequency ripple suppression capability.

Technical contradiction:

Ceramic capacitors (such as X7R) have low high-frequency impedance but limited capacity (usually<100 μ F)

Unable to effectively absorb low-frequency (<100kHz) ripple, resulting in intensified output voltage fluctuations

Solution:

Multi level filtering: ceramic capacitor (high frequency)+tantalum capacitor (medium frequency)+small polymer capacitor (low frequency)

Magnetic integration technology: Integrating output inductance and filtering capacitor into a single magnetic core to reduce parasitic parameters

Active filtering: Introducing an auxiliary LC network to dynamically compensate for ripple, but increasing control complexity